The invention generally relates to printed circuit board routing and power delivery for high frequency integrated circuits.
Referring to FIG. 1, a typical printed circuit board (PCB) 5 includes various conductive layers and a substrate, or core 12, that supports circuit components (mounted to the PCB 5) and the conductive layers of the PCB 5. As an example, in a four layer PCB configuration, two of the four layers may be located one side (called a “top side” for purposes of simplifying the discussion) of the core 12, and two layers may be located on the opposite, bottom side of the core 12.
As a more specific example, the PCB 5 depicted in FIG. 1 has four conductive layers, or is a “four layer PCB,” that includes such layers as a top signal layer 8, a layer that includes etched out conductive traces to route various communication signals that are associated with components that are mounted to the PCB 5 above the layer 8. The PCB 5 also includes a supply voltage plane layer 10 that is located between the signal layer 8 and the top side of the core 12. As its name implies, the supply voltage plane layer 10 provides a supply voltage to the various components that are mounted to the PCB 5, and like all layers beneath it, the layer 10 may be accessed by vertically extending vias (not shown). On the bottom side of the core 12, the PCB 5 includes a ground plane layer 14 that is located next to the core 12 and serves as a ground connection for the components that are mounted to the PCB 5. Adjacent to the ground plane layer 14 and forming the bottom layer of the PCB 5 is another signal layer 16 that, similar to the top signal layer 8, communicate various communication signals that are associated with components that are mounted to the PCB 5. All the above-described conductive layers of the PCB 5 are electrically isolated from each other via insulating layers 20.
Thus, in the PCB 5, the supply voltage plane 10 and ground plane 14 layers are separated by the relatively thick core 12 (as compared to the thickness of any of the conductive layers of the PCB 5), an arrangement that may introduce significant parasitic inductance. In this manner, when an electrical signal propagates along a trace on either the top 8 or bottom 16 signal layers, a return current is established to “close the loop” and make the net current flow equal to zero. This return current path selects the path of least resistance to flow in, and thus, the return current path tends to be routed through the ground plane layer 14. For an electrical signal propagating along a trace on the bottom signal layer 16, this is desirable because the return current path that is established is approximately the thickness of one of the insulating layers 20 (i.e., the thickness between the ground 14 and the bottom signal layer 16) to establish a relatively small parasitic inductance.
However, in contrast, for an electrical signal that propagates along the top signal layer 8, the return current loop is significantly larger due to the thickness of the intervening core 12. As an example, the effective inductance experienced along the path of the return current for a signal propagating along the top signal layer 8 may be about ten times the effective inductance than the inductance experienced by a signal propagating along the bottom signal layer 16. Such large inductances for signals of the top signal layer 8 may present challenges for a PCB design to be used with high frequency components, i.e., the components that are most susceptible to these large inductances.
Thus, there is continuing need for an arrangement to address one or more of the problems that are stated above.